Update development plan with vertical slice approach

- Reorder sprints for visual-first development
- Dashboard (Sprint 4) now follows Physics Engine (Sprint 3)
- Infrastructure layers (SCPI, TCP, HAL) follow visual demo
- Update project references to py-dvt-ate

docs/02_technical_specification.md

@@ -1,5 +1,5 @@
 # Technical Design Document
-## ThermalATE: Implementation Specification
+## py_dvt_ate: Implementation Specification
 
 | Document ID | TDD-001 |
 |-------------|---------|
@@ -13,7 +13,7 @@
 
 ## Purpose
 
-This document specifies **how** to implement the ThermalATE system. It contains technical details including architecture diagrams, code structures, interfaces, schemas, and specifications.
+This document specifies **how** to implement the py_dvt_ate system. It contains technical details including architecture diagrams, code structures, interfaces, schemas, and specifications.
 
 For **what** the system must do, see `01_requirements.md`.
 For **why** decisions were made, see `03_architecture_decisions.md`.
@@ -885,7 +885,7 @@ All instruments implement these standard commands:
 **Example Session**:
 ```
 > *IDN?
-< ThermalATE,VirtualChamber,SN001,1.0.0
+< py_dvt_ate,VirtualChamber,SN001,1.0.0
 > TEMP:SETPOINT 85.0
 > TEMP:SETPOINT?
 < 85.0
@@ -914,7 +914,7 @@ All instruments implement these standard commands:
 **Example Session**:
 ```
 > *IDN?
-< ThermalATE,VirtualPSU,SN002,1.0.0
+< py_dvt_ate,VirtualPSU,SN002,1.0.0
 > INST:SEL CH1
 > VOLT 5.0
 > CURR 0.5
@@ -944,7 +944,7 @@ All instruments implement these standard commands:
 **Example Session**:
 ```
 > *IDN?
-< ThermalATE,VirtualDMM,SN003,1.0.0
+< py_dvt_ate,VirtualDMM,SN003,1.0.0
 > CONF:VOLT:DC AUTO
 > SENS:VOLT:DC:NPLC 10
 > MEAS:VOLT:DC?